Presently, there is a great demand for shrinking semiconductor devices to provide an increased density of devices on the semiconductor chip that are faster and consume less power. The scaling of devices in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the thickness of the gate dielectric to be reduced so as to provide the required device performance.
On the other hand, there are several instances on a semiconductor chip where thicker gate dielectrics are still desired. For example, if the operating voltage is decreased, the device may no longer be compatible with most of the current packaged integrated circuits which operate at a standard voltage. For, instance, most circuits using CMOS transistors with gate lengths of 0.5 microns or more operate at 3.3V. When the gate length is decreased to 0.35 microns, the gate oxide thickness is reduced as well and the operating voltage is lowered to 2.5V or lower in order to maintain reliability of the gate oxide. Thus, a device may be needed that has input/output peripheral sections that operate at 3.3 V so that the device may be used in systems using other chips operating at 3.3 V while allowing other internal portions of the device to operate at 2.5 V. Other situations desiring dual gate dielectric thicknesses include: DRAMs in which a different gate dielectric thickness is desired for the high performance periphery versus the low leakage/low off-current array transistors; and embedded DRAMs which desire different thicknesses for transistors of the logic portion than for the DRAM transistors.
The seemingly most straightforward method of forming dual gate dielectric thicknesses is to grow a first gate oxide, resist pattern the first gate oxide, remove the exposed portions of the first gate oxide, remove the resist pattern, and then grow a second gate oxide. However, placing a resist pattern over the gate oxide and subsequently removing it can result in defects and contamination in the gate oxide as well as using twice the thermal budget of a single-thickness process.
One method used to form dual gate oxide thicknesses in a single chip without resist patterning the gate oxide, uses selective implantation of nitrogen into the substrate prior to oxidation (see, Soleimani et al, U.S. Pat. No. 5,330,920, issued Jun. 19, 1994). Nitrogen is used to retard the oxidation. Therefore, a patterned implant is used to implant nitrogen in areas where the thinner gate oxide is desired. Areas for thicker gate oxide transistors are not implanted. The pattern is then removed along with any sacrificial oxide. Then, the structure is oxidized to form the gate oxide having dual thicknesses. There are two difficulties in using this approach. First, implantation causes damage to the structure being implanted. Second, the nitrogen profile is difficult to control.
Another approach uses NH3 or N2O or NO thermal nitridation to form a nitride layer (see, Nakata, U.S. Pat. No. 5,254,489, issued Oct. 19, 1993). The nitride layer acts as an oxidation barrier and also nitrides the gate oxide. However, this approach requires high temperatures (in excess of 1000.degree. C. for NH3) and the difficulty in controlling the nitrogen profile remains.
Another approach uses two polysilicon layers (see, Tada, U.S. Pat. No. 5,497,021, issued Mar. 5, 1996). One polysilicon layer is placed over a first gate of one thickness. Next, a second gate oxide is grown and another polysilicon layer is deposited over the second gate oxide. This process however, adds too many additional process steps.